1. Field of the Invention
The present invention relates to an analog-to-digital converter for converting an analog signal to digital data, which is referred to simply as “A/D converter” hereinafter. In particular, the present invention relates to an A/D converter having a pulse delay circuit for sending a pulse signal while delaying the pulse signal in stages.
2. Description of the Related Art
A/D converters each including a pulse delay circuit having inverters connected in series and adapted to send a pulse signal while delaying it in stages have been well known. In particular, A/D converters each including a ring-gate delay circuit, as one type of the pulse delay circuit have also been well known. The ring-gate delay circuit has inverters serially connected in a ring.
Some of the A/D converters each including the ring-gate delay circuit are disclosed in, for example, U.S. Pat. No. 5,396,247 corresponding to Japanese Unexamined Patent Publication No. HS-259907, and U.S. Pat. No. 6,466,151 corresponding to Japanese Unexamined Patent Publication No. 2002-118467.
In addition, U.S. Pat. No. 6,509,861 corresponding to Japanese Unexamined Patent Publication No. 2002-217758 discloses an A/D converter including a non-circular pulse delay circuit, as another type of the pulse delay circuit, having inverters serially connected in a row. The A/D converter disclosed in U.S. Pat. No. 6,509,861 has a function of filtering off high-frequency noise components from a voltage signal Vin inputted to the non-circular pulse delay circuit. U.S. Pat. No. 6,255,976 corresponding to Japanese Patent Publication No. 3,292,182 discloses a sensor circuit including an A/D converter having such a pulse delay circuit and a method of eliminating low-frequency noise components caused in the sensor circuit. U.S. Pat. No. 5,416,444 corresponding to Japanese Unexamined Patent Publication No. H6-216721 discloses a ring-gate delay circuit, in other words, a ring oscillator, which has an even number of stages of inverters and is integratable with A/D converters.
The A/D converter disclosed in U.S. Pat. No. 6,466,151 is operative to convert a certain low level of an input voltage signal Vin to digital data. The A/D converter is composed of CMOS (Complementary Metal Oxide Semiconductor) transistors.
Various combinations of the CMOS transistors provide logic gates which perform particular logical functions, such as an inverter (NOT gate), an AND gate, an OR gate, a NAND gate, and so on.
FIG. 13 illustrates one of the inverters that constitute a component of the A/D converter disclosed in U.S. Pat. No. 6,466,151. As shown in FIG. 13, the inverter 300 is provided with a pair of complementary transistors (a p-channel transistor 100pT and an n-channel transistor 100nT). A power supply voltage, for example, VDDL is applied through a power supply line L100 to the p-channel transistor 100pT.
It is assumed that an input signal Ro having a voltage range between a high voltage level of Vin and a low voltage level of 0V [volts] is inputted to an input terminal 320 of the inverter 300, which is illustrated in FIG. 13. In FIG. 13, a period of time “a” indicates that the input signal Ro is kept at the low voltage level and a period of time “b”, that is, an excessive period, indicates that the input signal Ro is being turned from the low voltage level to the high voltage level. A period of time “c” indicates that the input signal Ro is kept at the high voltage level and a period of time “d”, in other words, an excessive period, indicates that the input signal Ro is being turned from the high voltage level to the low voltage level.
When the p-channel transistor 100pT is turned on and the n-channel transistor 100nT is turned off, a charging current Yb flows across the p-channel transistor 100pT out to a capacitance 360 between an output line 340 and a ground line L200.
When the p-channel transistor 100pT is turned off and the n-channel transistor 100nT is turned on, a discharging current Yc flows from the capacitance 360 into the n-channel transistor 100nT.
In addition, when both the p-channel transistor 100pT and the n-channel transistor 100nT are temporarily turned on, the switching operations of complementary transistors 100pT and 100nT may cause generation of a tunneling current Ya flowing between the power supply line L100 and the ground line L200. This tunneling current Ya may cause power consumption of the A/D converter to increase.